SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

26 October 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 294-295
https://doi.org/10.1109/vlsic.2004.1346592

Abstract

A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 /spl mu/m/sup 2/ 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.

Keywords

CMOS TECHNOLOGY
RANDOM ACCESS MEMORY
TIMING
LATCHES
INTEGRATED CIRCUIT TECHNOLOGY
CIRCUIT TOPOLOGY
DECODING
FREQUENCY SYNCHRONIZATION
SLEEP
MANUFACTURING

This publication has 1 reference indexed in Scilit:

Characterization of multi-bit soft error events in advanced SRAMs
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004