Synthesis and Comparison of Two's Complement Parallel Multipliers
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (10) , 1020-1027
- https://doi.org/10.1109/T-C.1975.224117
Abstract
A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication. The circuits are related to each other and to contemporary circuit algorithms in the course of the syntheses and in a comparative discussion. Circuits with complemented multiplier/multiplicand (M̄) or complemented partial product word (P̄) corrections offer advantages in circuit symmetry and algorithmic structure.Keywords
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