A module area estimator for VLSI layout
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Mason: A Global Floorplanning Approach for VLSI DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- PLEST: A Program for Area Estimation of VLSI Integrated CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Comparison of CMOS PLA and polycell representations of control logicPublished by Association for Computing Machinery (ACM) ,1986
- CHAMP: Chip Floor Plan for Hierarchical VLSI Layout DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985