Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing
- 17 August 2001
- book chapter
- Published by Springer Nature
- p. 441-450
- https://doi.org/10.1007/3-540-44687-7_45
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Rapid design of discrete cosine transform coresPublished by Institution of Engineering and Technology (IET) ,1998
- A single chip motion JPEG codec LSIIEEE Transactions on Consumer Electronics, 1997
- Hierarchical VHDL libraries for DSP ASIC designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Development of low power MPEG1/JPEG encode/decode ICIEEE Transactions on Consumer Electronics, 1997
- Image and Video Compression StandardsPublished by Springer Nature ,1997
- Behavioral Synthesis and Component Reuse with VHDLPublished by Springer Nature ,1997
- JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standardProceedings of the IEEE, 1995