A 50ns DSP with parallel processing architecture

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXX, 158-159
https://doi.org/10.1109/isscc.1987.1157130

Abstract

This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm²die.

Keywords

DIGITAL SIGNAL PROCESSING
PARALLEL PROCESSING
RANDOM ACCESS MEMORY
READ-WRITE MEMORY
AUTOMATIC CONTROL
REGISTERS
FILTERING
CIRCUITS
DATA PROCESSING
PIXEL

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