A Low cost, microprocessor compatible, 18.4 um/sup 2/,6-t bulk cell technology for high speed SRAMS

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 65-66
https://doi.org/10.1109/vlsit.1993.760247

Abstract

A unique low cost, microprocessor compatible, 0.5 /spl mu/m/sup 2/ 5V CMOS technology utilizing an 18.4 4m2 bulk 6T cell for high density, high speed SRAMs is described. Microprocessor compatibility is ensured by improving CMOS and inter-onnect area efficiency. A 256K SRAM is used to demonstrate the technology.

Keywords

METALS
RANDOM ACCESS MEMORY
THIN FILM TRANSISTORS
COMPLEXITY THEORY
LAYOUT
CMOS INTEGRATED CIRCUITS

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