A 700 Mb/s BiCMOS read channel integrated circuit
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 184-185,
- https://doi.org/10.1109/isscc.2001.912596
Abstract
A read channel IC achieves >1.5 dB SNR improvement over a 32/34 rate EPRML read channel at 2.8 user bit density. The 0.18 /spl mu/m BiCMOS chip operates up to 700 Mb/s with 1.8 W read mode power using 3.3 V analog and 1.8 V digital power supplies. The die area is 9.64 mm/sup 2/.Keywords
This publication has 1 reference indexed in Scilit:
- Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairsIEEE Journal of Solid-State Circuits, 1991