A means of reducing custom LSI interconnection requirements
- 1 October 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 7 (5) , 395-404
- https://doi.org/10.1109/JSSC.1972.1052899
Abstract
Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective circuits that naturally occur on such large circuit arrays, it has been necessary to customize each wafer's interconnection mask to its unique yield pattern. The authors examine in detail a means of using each mask set for perhaps several unique wafers, thus providing important custom routing and mask generation cost savings. In the case of pad relocation, only a single mask then comprises the entire custom mask set for several wafer arrays.Keywords
This publication has 3 references indexed in Scilit:
- Current Status of Large Scale Integration TechnologyIEEE Journal of Solid-State Circuits, 1967
- A discretionary wiring system as the interface between design automation and semiconductor array manufactureProceedings of the IEEE, 1967
- Cost-size optima of monolithic integrated circuitsProceedings of the IEEE, 1964