A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A 128k 6.5 ns access/5 ns cycle CMOS ECL static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 3.5 ns, 2 K×9 self timed SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Fast CMOS ECL receivers with 100-mV worst-case sensitivityIEEE Journal of Solid-State Circuits, 1988