A masterslice LSI for subnanosecond random logic

• 1 January 1977
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• Vol. XX, 108-109
• https://doi.org/10.1109/isscc.1977.1155689

Abstract

Keywords

• LARGE SCALE INTEGRATION
• WIRING
• LOGIC CIRCUITS
• PINS
• LOGIC DESIGN
• DELAY
• RESISTORS
• LATCHES
• MULTIPLEXING
• POWER DISSIPATION