Testing of UltraSPARC T1 Microprocessor and its Challenges
- 1 October 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2006 IEEE International Test Conference
- No. 10893539,p. 1-10
- https://doi.org/10.1109/test.2006.297637
Abstract
This paper presents the testing methodology of the UltraSPARC T1 microprocessor and the challenges to productizing the industry's first 8 cores and 32 thread microprocessor. The challenges include effectively testing 8 individual cores that share common functional blocks (L2 cache, cache crossbar, floating point unit), reducing 8times conventional production test time and tester memory while achieving the same coverage, and productizing 6 core or 8 core devices at the targeted frequency. Highlights of DFT features designed to overcome the challenges are presented followed by a production flow together with key learning and future improvement plansKeywords
This publication has 4 references indexed in Scilit:
- Sun's big splash [Niagara microprocessor chip]IEEE Spectrum, 2005
- Testing static and dynamic faults in random access memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Debug methodology for the McKinley processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Designing UltraSparc for testabilityIEEE Design & Test of Computers, 1997