Refractory self-aligned gate technology for GaAs microwave FETs and MMICS

24 September 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (20) , 1073-1075
https://doi.org/10.1049/el:19870750

Abstract

A new refractory self-aligned gate technology for fabrication of field-effect transistors (FETs) with low gate resistance and improved breakdown voltage is described. The asymmetric-n⁺, planarised-gate process uses 1 μm optical lithography to produce 0.5 μm-gate-length FETs with very low gate resistance. The process is suitable for high-volume small-signal and power MMIC production.

Keywords

LOW GATE RESISTANCE
MONOLITHIC MICROWAVE IC
MMIC PRODUCTION
0.5 MICRON
IMPROVED BREAKDOWN VOLTAGE
SUBMICRON GATE LENGTH
GAAS
REFRACTORY SELF-ALIGNED GATE TECHNOLOGY
FABRICATION
III-V SEMICONDUCTORS
SAG
ASYMMETRIC N+ IMPLANT
1 MICRON
MANUFACTURE
OPTICAL LITHOGRAPHY
FIELD-EFFECT TRANSISTORS
MICROWAVE FETS