I ddq secondary components in CMOS logic circuits preceded by defective stages affected by analogue type faults

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Abstract
Certain physical failures produce abnormal voltages at the output of the defective stages. Iddq testing techniques are shown to be efficient in testing for these failures. Because of the intermediate analogue output of the faulty stage, posterior fault-free stages exhibit abnormal values of Iddq, increasing the effect of the fault. The set of stages influenced by the fault is modelled and analysed presenting characteristics of the propagation of the influence.

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