A pipelined 32b microprocessor with 13Kb of cache memory

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXX, 34-35
https://doi.org/10.1109/isscc.1987.1157124

Abstract

A Reduced Instruction Set Computer containing 172K transistors in 1.5μm technology will be described. The chip contains caches for prefetch buffer, decoded instructions and stack. Two internal machines with three pipelined stages are used.

Keywords

MICROPROCESSORS
CACHE MEMORY
CIRCUITS
CLOCKS
REGISTERS
CMOS TECHNOLOGY
DECODING
VERY LARGE SCALE INTEGRATION
CENTRAL PROCESSING UNIT
INFORMATION SYSTEMS

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