A 15MIPS 32b microprocessor

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXX, 26-27
https://doi.org/10.1109/isscc.1987.1157220

Abstract

A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMOS technology is used to implement 115K transistors on an 8.4mm square chip.

Keywords

MICROPROCESSORS
CLOCKS
PIPELINES
CIRCUITS
DECODING
PROGRAMMABLE LOGIC ARRAYS
CACHE MEMORY
FREQUENCY
REGISTERS
CENTRAL PROCESSING UNIT

This publication has 0 references indexed in Scilit: