Timing Accuracy in Modern ATE
- 1 April 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 4 (2) , 22-30
- https://doi.org/10.1109/MDT.1987.295102
Abstract
LSI test systems built in the 1970s had compact, 60-pin test heads that presented devices under test with open wires leading to lumped-capacitive loads. Today's VLSI testers have 256-pin test heads with transmission lines leading from the DUTs to driver-comparator circuits that are as far away as 50 cm. Even though these automatic testers are adjusted to subnanosecond accuracy, reflections within the transmission lines can cause timing measurement errors up to 10 ns for MOS devices whose output impedances are not matched to the transmission lines. The authors offer the Advice circuit simulator (an AT&T proprietary version of SPICE) as one way to analyze errors due to transmission line problems before testing. They also discuss ways to correct timing errors. Finally, they recommend that very high speed ICs be designed to drive transmission lines that are terminated with matched resistors at the comparators.Keywords
This publication has 1 reference indexed in Scilit:
- Fundamental Timing Problems in Testing MOS VLSI on Modern ATEIEEE Design & Test of Computers, 1984