Analysis of electric field distribution in GaAs metal–semiconductor field effect transistor with a field-modulating plate

Electric field distribution in the channel of a field effect transistor (FET) with a field-modulating plate (FP) has been theoretically investigated using a two-dimensional ensemble Monte Carlo simulation. This analysis revealed that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric field intensity at the drain side of the gate edge under pinch-off bias conditions. This study also found that a partial overlap of the high-field region under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal–semiconductor FET with FP (FPFET) ${\mathrm{(L}}_{\mathrm{GF}}\text{∼0.2\hspace{0.05em}μ}\mathrm{m})$ exhibited a much lower peak electric field intensity than a conventional metal–semiconductor FET. Based on these numerically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while maintaining reasonable gain performance.