LOW POWER DESIGN OF OFF-CHIP DRIVERS AND TRANSMISSION LINES: A BRANCH AND BOUND APPROACH

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Abstract
As electronic systems grow in functional complexity, hence size, the design is often forced into a multi-chip solution. For such systems, the power dissipation due to the off-chip drivers (OCDs) and the off-chip interconnect capacitance can contribute to a significant portion of the overall system power. Often, however, this excessive power dissipation is unwarranted, since a smaller OCD can be used to drive the transmission line load, hence reducing the net capacitance being switched. The objective of this paper is to enable power dissipation trade-off decisions during the high-level phases of design and to minimize the power dissipation of OCDs and their associated interconnect. First, a termination metric is described that uses width optimization of RLC interconnects. Then, in terms of a proposed linear driver model, the low power design objective is posed as an integer programming problem and a branch and bound enumeration algorithm is presented. The driver and interconnect sizes are determined which will preserve signal quality, dispense with additional termination components, meet delay requirements, and minimize the overall power dissipation.

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