Automatic VLSI Layout Verification

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Abstract
Xerox has instituted a set of software tools that close the loop between circuit design and mask generation of VLSI and provide checks and analysis along the way. The software includes circuit extraction, capacitance calaulation, nodal analysis and logic recognition as well as interfaces to graphic systems. The systematic method of capturing circuit designs and the software packages for analyzing mask data are described in this paper. The kinds of errors checked and the method of reporting errors are explained. This paper traces a single design from circuit description to mask making. It shows all the check points and verification tools presently available to a designer at Xerox. The example used for demonstration is the design of a small component of a chip called a cell. It should be pointed out that the tools described are not restricted to cell verification. For the most part they will accommodate up to full chip designs.

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