Systolic random number generation for genetic algorithms
- 6 June 1996
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 32 (12) , 1069-1070
- https://doi.org/10.1049/el:19960709
Abstract
A parallel hardware random number generator for use with a VLSI genetic algorithm (GA) processing device is proposed. The design uses a systolic array of mixed congruential random number generators. The generators are constantly reseeded with the outputs of the proceeding generators to avoid significant biasing of the randomness of the array, which would result in longer times for the algorithm to converge to a solution.Keywords
This publication has 1 reference indexed in Scilit:
- Parallel random number generation for VLSI systems using cellular automataIEEE Transactions on Computers, 1989