High performance VLSI architecture for division and square root
- 3 January 1991
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 27 (1) , 19-21
- https://doi.org/10.1049/el:19910013
Abstract
A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.Keywords
This publication has 1 reference indexed in Scilit:
- Implementation of module combining multiplication, division, and square rootPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003