Stacked CMOS SRAM cell

1 August 1983

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 4 (8) , 272-274
https://doi.org/10.1109/edl.1983.25730

Abstract

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

Keywords

RANDOM ACCESS MEMORY
SILICON
COATINGS
POWER LASERS
LASER MODES
CIRCUIT TESTING
ETCHING
THERMAL STRESSES
THRESHOLD VOLTAGE
MOS DEVICES

This publication has 0 references indexed in Scilit: