Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile
- 30 August 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Rate-constrained coder control and comparison of video coding standardsIEEE Transactions on Circuits and Systems for Video Technology, 2003
- Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standardIEEE Transactions on Circuits and Systems for Video Technology, 2003
- An entropy coding system for digital HDTV applicationsIEEE Transactions on Circuits and Systems for Video Technology, 1991