Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors

1 January 1977

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1977.189225

Abstract

An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.

Keywords

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