Specification, Simulation and Automated Design of Interfaces and Digital Circuits.

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Abstract
This report describes research done in hardware description, simulation, and design automation. Although the basic thrust of the work has been aimed at I/O and interface problems, most of the results are more general. The efforts in formal hardware description have produced a language for bus, I/O and interface specification, GLIDE. GLIDE is supported by a compiler which performs syntactic and semantic checks. A translator to the ISPL language has also been written. The resulting code and non-translatable GLIDE semantics forced abandonment of ISPL either directly or indirectly from GLIDE for I/O description. The major research reported here is design automation work. This grant has supported synthesis research - the mapping from a functional description of the system (ISP) to be designed to the structure. Automated design of the control circuitry is in the early stages, but a working program designs the data paths, registers and memories. An early design the program produced came within 25% of the cost of the design a human designer produced. The PDP-8/E design, included here, has a chip count within 50% of that commercial design, but the design program produced an entirely different design.

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