CMOS design technique to eliminate the stuck-open fault problem of testability

13 September 1984

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 20 (19) , 758-760
https://doi.org/10.1049/el:19840516

Abstract

A dynamic CMOS design style is described, which utilises both N-type and P-type logic blocks and avoids the problems in generating tests for stuck-open faults. The testability of the resultant logic is examined analytically and fault simulation results are presented.

Keywords

TESTABILITY
N-TYPE LOGIC BLOCKS
LOGIC DESIGN
GENERATING TESTS FOR STUCK-OPEN FAULTS
P-TYPE LOGIC BLOCKS
VLSI
STUCK-OPEN FAULT PROBLEM
FAULT SIMULATION RESULTS
DYNAMIC CMOS DESIGN STYLE
LOGIC TESTING
TEST PROBLEM ELIMINATION
NORA CMOS

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