Two-dimensional modelling of s.o.s. transistors
- 1 January 1978
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Journal on Solidstate and Electron Devices
- Vol. 2 (2) , 47-51
- https://doi.org/10.1049/ij-ssed.1978.0008
Abstract
The paper presents a 2-dimensional numerical model used to analyse the silicon-on-sapphire transistor under various geometries, doping levels and bias conditions. The model accounts for the thin-film structure and the finite interface charge at the silicon-sapphire interface. The model also includes the possibility of simulating nonisothermal effects, and is shown to be applicable to prediction of the transistor behaviour in the high-voltage region. The complete system of four coupled partial differential equations describing the internal behaviour of the s.o.s. transistor is solved exactly. Typical results for an n-channel double-implanted inversion-layer s.o.s. transistor are shown. The agreement between theory and experiment is found to be excellent.Keywords
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