A parallel arithmetic unit using a saturated-transistor fast-carry circuit
- 1 January 1960
- journal article
- Published by Institution of Engineering and Technology (IET) in Proceedings of the IEE Part B: Electronic and Communication Engineering
- Vol. 107 (36) , 573-584
- https://doi.org/10.1049/pi-b-2.1960.0171
Abstract
The paper describes a transistor switch technique which is of particular importance in applications where a large number of switches have to be connected in series and where the propagation time of information through these switches has to be a minimum. It is thus of importance in parallel addition, and its use in this connection has been successfully demonstrated, yielding an addition time over 24 digits of 200 millimicrosec. The technique is reasonably economical, and the paper also shows how it can be used in conjunction with more conventional logical circuits to provide a simple arithmetic unit.Keywords
This publication has 1 reference indexed in Scilit:
- Ferrite-core memory systems with rapid cycle timesProceedings of the IEE Part B: Electronic and Communication Engineering, 1960