Comments on "Inner Product Computers"
- 1 December 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-28 (12) , 944
- https://doi.org/10.1109/tc.1979.1675288
Abstract
The results for different hardware configurations of inner product computers presented by Swartzlander et al.1 are in error. In their Table I, the pipelined quasi-serial processor is credited with the ability to evaluate a complete inner product in 10 ns. The clock rate may be 10 ns but several clocks are required to evaluate one inner product. (Note the serial adder feeding the result register in their Fig. 2.)Keywords
This publication has 1 reference indexed in Scilit:
- Inner Product ComputersIEEE Transactions on Computers, 1978