Influence of polysilicon gate formation conditions on thin gate oxide (4–6 nm) dielectric and charging properties

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Abstract
The influence of poly-Si gate formation conditions on the electrical properties and reliability of very thin thermal SiO2 films is described. Phosphorus-doped (P) poly-Si, phosphorus ion (P+) implanted poly-Si, and arsenic ion (As+) implanted poly-Si are used as metal-oxide-semiconductor capacitor gates for comparison. Long-term bias temperature aging tests show that As+ poly-Si is the most stable of the three gates from the standpoint of minimum flatband voltage shift. It is shown that electron trapping probability in the oxides is extremely low compared with that of hole trapping. This result is closely related to a mechanism in which electron tunneling distance in the oxides is 3 nm and electrons trapped in oxides thinner than 6 nm detrap easily to the oxide exteriors. Furthermore, it is shown that long-term avalanche injection of electrons induces electron trapping for 6-nm-thick oxides which are free from electron trapping under ordinary stressing conditions. The capture cross section of this electron trapping is estimated to be about 6×10−22 cm−2, three or four orders of magnitude lower than the values already reported. It is thought that the energy level of this trap center is deeper than 3.1 eV below the SiO2 conduction band edge.

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