Test-point condensation in the diagnosis of digital circuits

Abstract
The paper shows how simple circuitry can be used to combine test points leading to far fewer points to be observed, while still retaining the full ability to detect faults. Rules are laid down for the design of this circuitry that depend on the relationship between the test points. Practical examples are given of circuits for condensing test points for a number of different circumstances. Finally, it is shown how the adequate testing of this additional condensing circuitry can be ensured.