A model for conduction in floating-gate EEPROM's

Abstract
A model of conduction between two levels of polysilicon separated by thermally grown oxide in a floating-gate EEPROM structure is described. For the model, a modified Fowler-Nordheim description of the tunnel current is used to include the effects of localized-field enhancement and localized-tunneling area. The threshold voltage as a function of time during the erase transient is derived and the degradation of the conduction efficiency with increasing write-erase cycles is modeled by extention of the model parameters to include the effects of trapped charge. Both the centroid of the charge and the parameters to describe the trap distribution with respect to the capture cross section are included. Experimental results are used to determine the model parameters and prediction of endurance and retention is discussed.

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