Record RF performance of 45-nm SOI CMOS Technology
Top Cited Papers
- 1 December 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 255-258
- https://doi.org/10.1109/iedm.2007.4418916
Abstract
We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.Keywords
This publication has 1 reference indexed in Scilit:
- Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS ProcessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007