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Trench Isolation Technology for 0.35/spl mu/m Device by Bias ECR CVD
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Trench Isolation Technology for 0.35/spl mu/m Device by Bias ECR CVD
Trench Isolation Technology for 0.35/spl mu/m Device by Bias ECR CVD
TG
T. Gocho
T. Gocho
YM
Y. Morita
Y. Morita
JS
J. Sato
J. Sato
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1 January 1991
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
p.
87-88
https://doi.org/10.1109/vlsit.1991.706003
Abstract
No abstract available
Keywords
ISOLATION TECHNOLOGY
ETCHING
PLANARIZATION
DIODES
FLUID FLOW
LEAKAGE CURRENT
ULTRA LARGE SCALE INTEGRATION
RESEARCH AND DEVELOPMENT
BUFFER LAYERS
PROTECTION
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