An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 136-145
- https://doi.org/10.1109/isca.1992.753311
Abstract
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there are functional unit conflicts. This parallel execution scheme greatly improves the utilization of the functional unit. Simulation results show that by executing two and four threads in parallel on a nine-functional-unit processor, a 2.02 and a 3.72 times speed-up, respectively, can be achieved over a conventional RISC processor. Our architecture is also applicable to the efficient execution of a single loop. In order to control functional unit conflicts between loop iterations, we have developed a new static code scheduling technique. Another loop execution scheme, by using the multiple control flow mechanism of our architecture, makes it possible to parallelize loops which are difficult to parallelize in vector or VLIW machines.Keywords
This publication has 12 references indexed in Scilit:
- Exploring The Benefits Of Multiple Hardware Contexts In A Multiprocessor Architecture: Preliminary ResultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Can Dataflow Subsume Von Neumann Computing?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Toward a dataflow/von Neumann hybrid architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- MASA: a multithreaded processor architecture for parallel symbolic computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A processor architecture for HorizonPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Boosting beyond static scheduling in a superscalar processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- APRIL: a processor architecture for multiprocessingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Strategies for achieving improved processor throughputPublished by Association for Computing Machinery (ACM) ,1991
- Software pipelining: an effective scheduling technique for VLIW machinesPublished by Association for Computing Machinery (ACM) ,1988
- A Fortran compiler for the FPS-164 scientific computerPublished by Association for Computing Machinery (ACM) ,1984