Monolithic 1.6 Gbit/s 8:1 Multiplexer and 1:8 Demultiplexer Subsystems using CDFL

1 November 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 079-082
https://doi.org/10.1109/gaas.1985.10399519

Abstract

This paper describes a fully ECL compatible 1.6 Gbit/s multiplexer (MUX) and companion demultiplexer (DEMUX) intended for use in fiber optic communication systems, RF memories, and high speed display applications. The circuits were fabricated using GigaBit's standard planar GaAs IC process, and characterized with respect to system performance. Each chip has approximately 200 equivalent logic gates and a power dissipation less than 1.5 W at the 1.6 GHz clock frequency. The Capacitor Diode-Coupled FET Logic (CDFL) approach was used to achieve good speed power product performance.

Keywords

CLOCKS
MULTIPLEXING
INTEGRATED CIRCUITS
GALLIUM ARSENIDE
SYNCHRONIZATION
PINS
STREAMS

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