Self-aligned contact schemes for source-drains in submicron devices

1 January 1987

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1987.191430

Abstract

This paper reviews the basic limitations in source-drain parasitics and source-drain contacts as devices are scaled to the submicron regime. The major portion of the paper reviews the various proposals to provide local interconnect layers which interface with the source-drain and from which all contact windows to metal-1 are made over field oxide. Among the promising approaches are HPSAC, TiN local interconnect, BOMOS and UPMOS. Significant improvements in parasitic reduction, layout density, and reliability can be achieved.

Keywords

CONTACT RESISTANCE
SILICIDES
TIN
PARASITIC CAPACITANCE
DOPING PROFILES
SURFACE RESISTANCE
PROPOSALS
SILICON DEVICES
MOSFET CIRCUITS
PLUGS

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