Experimental 1 Mbit DRAM using power reduction techniques
- 1 January 1985
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings I Solid State and Electron Devices
- Vol. 132 (1) , 23-28
- https://doi.org/10.1049/ip-i-1.1985.0006
Abstract
One of the serious problems which must be overcome in realising a 1 Mbit DRAM is high-power dissipation associated with data-line charging and discharging. To solve this problem, this paper proposes the following three techniques, which permit power reduction by about one-quarter: a multidivided data-line structure, 512 refresh cycles and an on-chip voltage limiter circuit. These techniques are proven to be useful through the design and evaluation of an experimental n-MOS 1 Mbit DRAM with a 46 mm2 chip size. The chip fabricated provides a 295 mW operating power at a 260 ns cycle time despite the fast access time of 90 ns. The possibility of further power reduction is also described.Keywords
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