Analysis of Limit Cycles in a Two-Transistor Saturable-Core Parallel Inverter
- 1 July 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Aerospace and Electronic Systems
- Vol. AES-9 (4) , 571-584
- https://doi.org/10.1109/taes.1973.309641
Abstract
A familiar two-transistor saturable-core parallel inverter is modeled as a nonlinear negative resistance in parallel with energy-storage elements. The techniques of singular-point analysis are combined with piecewise linear techniques to permit determination of solution trajectories on the phase plane. Clear insight is provided, not only into steady-state oscillation, but also into transient behavior of the circuit. Experimental results confirming the analytical model are included.Keywords
This publication has 1 reference indexed in Scilit:
- A High-Speed Two-Winding Transistor Magnetic-Core OscillatorIRE Transactions on Circuit Theory, 1957