Validating discrete event simulations using event pattern mappings
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 414-419
- https://doi.org/10.1109/dac.1992.227768
Abstract
This paper introduces a new concept for the validation of discrete event simulations, based on recursively detecting and naming patterns of events. This paper introduces language constructs for dejining event patterns (VAL+ mappings,), explains the methodology for validating a design using event patterns, describes a softwaw tool based on mappings (VAL+ debugger) and lists results of using the debugger on three larger examKeywords
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