An LSI adaptive array processor

Abstract
Describes an LSI adaptive array processor (AAP) for two-dimensional data processings. The AAP contains a large number of one-bit processing elements (PEs) arranged in a square array. The large degree of parallelism and control registers in each PE allow for high speed and flexible operations. High transfer capability is also obtained by a simple inter-PE connection network with hierarchical bypasses. The high applicability to various data processings is indicated by a matrix multiplication example, utilizing an algorithm similar to a systolic one. An AAP LSI composed of 8/spl times/8 PEs with powerful functions has been implemented in a 96.0 mm/SUP 2/ chip by using 2 /spl mu/m Si-gate p-well CMOS technology. A high-speed cycle time of 55 ns, low power dissipation of 1.1 W, and high packing density of 1170 transistors/mm/SUP 2/ has been achieved by a skilful manual design. Though the LSI contains as many as 111900 transistors, the design effort has only required one man-year due to cellular array regularity. This LSI is expected to realize a high-performance AAP compactly.

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