Simultaneous delay and maximum current calculation in CMOS gates
- 26 March 1992
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 28 (7) , 682-684
- https://doi.org/10.1049/el:19920431
Abstract
An accurate and simple technique is presented for computing the delay and the maximum switching current in CMOS gates. The effects of input slope, output load, transistor size, and short circuit current are accounted for. The accuracy is within 10% of the SPICE level-3 model and the speed is more than three orders of magnitude faster than SPICE.Keywords
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