Expressing dynamic reconfiguration by partial evaluation
- 1 January 1996
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 188-194
- https://doi.org/10.1109/fpga.1996.564830
Abstract
Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment.Keywords
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