A theory of high-speed clocked logic
- 1 January 1965
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 150-161
- https://doi.org/10.1109/focs.1965.2
Abstract
In this paper we concern Ourselves with the problem of obtaining high sequence rate sequential machines, machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a Construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devices. Once a complete set of synchronous devices is obtained, the results of Arden and Arthurs1,2 apply and we know that any finite state machine has a realization using these devices which accepts input sequence members at a rate which is characteristic of the set of devices, not of the machine. The technique we propose for achieving this result is to produce a lattice of interconnected clock pulse sources called Clock Pulse Propagators. These devices generate clock pulses which are acceptably synchronized with respect to the outputs of neighboring CPP's but are not required to be in synchronization with some machine-wide standard as in current practice. Once it is established that such a network is possible, techniques already known can be applied in the utilization of the clock-pulses to synchronize logic and signals. In this paper, we first present and analyze the use of the assumed clock pulses to synchronize the logic. Lower bounds are developed for the clock-pulse period which depend on the logic device parameters, signal propagation delay and delay variation, and on the size of the region that each CPP serves. As a consequence of this analysis, it is found that in some circumstances, the two phase clock has the potential for higher rate operation than the single phase and is less restrictive in the design constraints imposed for stable operation. The other major portion of the paper is devoted to the presentation of the nature of the CPP, a device based strongly on McNaughton's RBF element3, and the proof that a network of these devices does produce acceptably synchronous clock pulses.Keywords
This publication has 3 references indexed in Scilit:
- Completeness of Sets of Delayed-Logic DevicesIEEE Transactions on Electronic Computers, 1965
- Antiparallel control logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1964
- The synthesis of sequential switching circuitsJournal of the Franklin Institute, 1954