Concurrent error detection/correction in the HAL MMU chip

• 30 December 2002
• proceedings article
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• https://doi.org/10.1109/ftcs.1993.627366

Abstract

Keywords

• CHIP
• ERROR CORRECTION
• MEMORY MANAGEMENT
• MEMORY MANAGEMENT UNIT
• COLLABORATIVE SOFTWARE
• HARDWARE
• CONTENT ADDRESSABLE MEMORY
• INDEXING TERMS
• CACHE ARCHITECTURE
• CONCURRENT COMPUTING
• COMPUTER ARCHITECTURE