A 35 ns 16K NMOS static RAM
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (5) , 815-820
- https://doi.org/10.1109/jssc.1982.1051824
Abstract
An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.Keywords
This publication has 4 references indexed in Scilit:
- A 35ns 16K NMOS static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A 25ns 16 × 1 static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- 2K×8b HCMOS static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- Fully static 16Kb bulk CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980