A dynamic-trace-driven simulator for evaluating parallelism

1 January 1988

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 158-166
https://doi.org/10.1109/hicss.1988.11761

Abstract

An efficient simulation method is presented that can model the performance of a given algorithm on an idealized multiprocessor while modeling state changes by executing equivalent code on a host processor. Characteristics of the target multiprocessor can be defined independently of the algorithm specification permitting the evaluation of an algorithm over several different machines, or conversely, the performance of a given machine for differing workloads. Performance metrics relating to both hardware and software overheads can be recorded during any given simulation run. The simulator is efficient enough to be run interactively on a current-model superminicomputer.

Keywords

HARDWARE
ANALYTICAL MODELS
ALGORITHM DESIGN AND ANALYSIS
PERFORMANCE ANALYSIS
COMPUTATIONAL MODELING
PARALLEL ALGORITHMS
PARALLEL PROCESSING
TIMING
CONCURRENT COMPUTING
COMPUTER SCIENCE

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