Test Program Generation for Functional Verification of PowePC Processors in IBM
- 1 December 1995
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the 39th conference on Design automation - DAC '02
- p. 279-285
- https://doi.org/10.1109/dac.1995.249960
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- DACCT-dynamic ACCess testing of IBM large systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Logical verification of the NVAX CPU chip designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Constraint solving for test case generation: a technique for high-level design verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generatorIBM Systems Journal, 1991