Verification of a multiprocessor cache protocol using simulation relations and higher-order logic
- 1 December 1992
- journal article
- Published by Springer Nature in Formal Methods in System Design
- Vol. 1 (4) , 355-383
- https://doi.org/10.1007/bf00709156
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- The existence of refinement mappingsTheoretical Computer Science, 1991
- Formal verification of data type refinement — Theory and practicePublished by Springer Nature ,1990
- Analysis of discrete event coordinationPublished by Springer Nature ,1990
- Correctness Properties of the Viper Block Model: The Second LevelPublished by Springer Nature ,1989
- Trace Theory for Automatic Hierarchical Verification of Speed-Independent CircuitsPublished by MIT Press ,1989
- Hierarchical correctness proofs for distributed algorithmsPublished by Association for Computing Machinery (ACM) ,1987
- Automatic Verification of Sequential Circuits Using Temporal LogicIEEE Transactions on Computers, 1986