Hierarchical Top-Down Layout Design Method for VLSI Chip
- 1 January 1982
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- An automatically designed 32b CMOS VLSI processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC MasksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Methods for Hierarchical Automatic Layout of Custom LSI Circuit MasksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- A “Dogleg” channel routerPublished by Association for Computing Machinery (ACM) ,1976
- Wire routing by optimizing channel assignment within large aperturesPublished by Association for Computing Machinery (ACM) ,1971